CPU Topology Inspector

CPU Topology Inspector is a desktop processor topology mapper, cache-sharing visualizer, instruction set extension matrix, and memory hierarchy micro-probe for Linux workstations and servers. A lightweight Linux alternative to Sysinternals Coreinfo, it reads live processor, cache, NUMA, frequency, and ISA metadata directly from the Linux kernel (/proc/cpuinfo and /sys/devices/system) with zero synthetic or placeholder data.

Key Features:

• Package, Core, SMT & Cache Sharing Map: Reads live physical package, die, core, and logical thread sibling mappings alongside L1d, L1i, L2, and L3 cache ways, line sizes, set counts, shared CPU masks, and NUMA node memory domains, rendering a visual processor topology diagram.
• ISA Instruction Set & Hardware Mitigation Matrix: Audits real CPU feature flags across SIMD/Vector (SSE through AVX2, AVX-512, FMA, NEON/SVE), cryptographic offload (AES-NI, PCLMULQDQ, SHA-NI, RDRAND, RDSEED), virtualization (VMX, SVM, Hypervisor), and bit-manipulation extensions alongside kernel hardware mitigation states with instant search filtering.
• Cache Latency Micro-Benchmark & Export: Runs a pure-Python pointer-chasing access latency and memory-stride bandwidth probe across L1 (16 KB), L2 (256 KB), L3 (4 MB), and DRAM (32 MB) working sets and exports complete JSON and CSV topology reports.

Disclaimer: This project is an independent open-source tool and is not affiliated with, sponsored by, or endorsed by Microsoft Corporation or Sysinternals.